Archive · 25 Sep 2026
IIT Delhi Researchers Develop India’s First Indigenous Micro-GPU
IIT Delhi researchers built a small computer design called a micro-GPU.
A GPU helps computers create images and supports artificial-intelligence and machine-learning systems.
The team says this is India’s first working, demonstrable indigenously designed micro-GPU from a university.
They tested it by putting its design on a programmable Spartan-7 FPGA.
This means the device can be programmed to render graphics.
It is intended for affordable embedded devices such as dashboards, displays, and e-readers.
The researchers want to expand it into an 8-16-core processor and create supporting software.
They also hope to make a version using a 65 nm ASIC process.
The team is seeking funding to continue development and eventually commercialize the technology.
IIT Delhi researchers developed a working, demonstrable indigenously designed micro-GPU.
The programmable graphics engine was implemented in RTL and mapped to a Spartan-7 FPGA.
The architecture targets affordable embedded applications, including industrial displays, dashboards, navigation terminals, and e-readers.
The team is exploring an 8-16-core vector-style processor, optimized software, and a 65 nm ASIC proof of concept.
Researchers are seeking funding for ASIC development, system integration, and eventual commercialization.
- Who
- MTech students Nammi Akash and Ravi Teja led the project under Professors Jayadeva and Kaushik Saha at IIT Delhi.
- What
- They developed a working, demonstrable indigenously designed micro-Graphics Processing Unit.
- When
- The article does not specify when the micro-GPU was developed.
- Where
- The work was conducted in the Electrical Engineering Department of IIT Delhi, India.
- Why
- The project aims to reduce dependence on imported GPU technology and support affordable embedded visualisation systems.
- Institution
- Indian Institute of Technology Delhi
- Technology
- Programmable micro-Graphics Processing Unit
- Implementation
- Custom floating-point GPU engine implemented in Register Transfer Language
- Test platform
- Spartan-7 Field-Programmable Gate Array
- Planned architecture
- 8-16-core vector-style graphics processor
- Planned process
- 65 nm application-specific integrated circuit proof of concept
- Funding sought
- ASIC development, system integration, and eventual commercialisation